Project Update
May 12, 2022
Fabricating MOSFETs
We design a process sequence to make a MOSFET, implement the process, characterize the device performance based on the thin film thicknesses, and correlate device behavior with the quality of the processes used to fabricate the device.
Project Dates: April 2022 - May 2022
Comparisson of the theoretical and actual post-etch gate oxide and gate. Actual image taken on a 10x microscope setting.
As the capstone project of ENG 177: Microfabrication Lab, I worked with a team to walk through all the steps of implementing a device, from designing a process sequence to correlate device behavior with the quality of the processes used to fabricate the device.
The core of the device is an enhancement-mode n-channel device formed on a p-type Si substrate. The n+ source and drain regions are diffused into a relatively lightly doped p-type substrate, and a thin oxide layer separates the conducting gate from the Si surface. No current flows from the drain to the source region without a conducting n channel between them. There is a potential barrier for an electron to go from the source to the drain, corresponding to the built-in potential of the back-to-back p-n junctions between the source and drain.
Left: schematic of a typical MOSFET device. Right: graphical overview of the formation of the Field Oxide Isolation process.
Formation of the Field Oxide Isolation
With the first mask, we defined and etched windows into the field oxide on which we built our MOSFETs. After the development process, we ensured the quality of the pattern using a microscope. For the etching step in this process, we used BOE 7:1. While BOE does not etch the p-doped Si wafer, it has a significant lateral etch rate and thus requires a calibration process. To calibrate the etch time for the MOSFET wafer, we broke a sample wafer into four pieces approximately 0.5 cm by 1 cm and etched one piece for each of the following times: 60s, 90s, 120s, 180s. We then measured the thickness of the remaining field oxide optically using a luxometer.
Unfortunately, the BOE 7:1 etched much faster than we expected when choosing our calibration times and seemed to reach the p-doped Si interface between 90s and 120s. As a result, we could only use the 60s and 90s samples for the calibration. Based off of these calibrations and the measured field oxide thickness of 120 nm, we etched the MOSFET wafer for 105s. We confirmed that we had etched to the p-doped Si interface using a luxometer and checked the quality of the etch using the microscope, as seen in the figure below.
Formation of the Source and Drain Contacts
We deposited approximately 300 nm of n-doped silicon using PECVD. We measured the thickness of the film using ellipsometry. However, because the system has a bilayer of thin films, the fit was more difficult and the measurements have a larger uncertainty. We used a second mask and lithography to create the desired source and drain pattern. Finally, we used an etch using 10:1 nitirc acid and hydroflouric acid to remove the excess Si and reveal our source and drain structures.
We included 5 chips in the PECVD machine alongside our sample to perform a calibration of the wet etch. However, we found that the etch rate was much faster than expected and would etch in to the Si etch times longer than 30 seconds. We found that it would be easier to visually see the transition from the dull grey Si that was deposited to the iridescent SiO2 to know when to end the etch.
Left: graphical representation of the formation of the Source and Drain Contacts. Right: graphical representation of the formation of Gate Oxide and Gate.
Formation of Gate Oxide and Gate
The formation of the gate oxide and the gate involves three steps. First, we perform the deposition of the 10 nm of SiO2 via the process called atomic layer deposition. Next, we perform PECVD depositing of 150 nm of n-doped Silicon. This specifically defines the gate material. Next, we define the gate region by performing a positive resist pattern with a particular mask (Mask 3). We then etched the wafer using 10:1 HNO3:HF for a short amount of time until we saw the color change, indicating we had etched through the gate oxide. Finally, we lifted off the mask and observed the results under the microscope.
Formation of Metal Contacts to the Device
Note that since ALD involves self-limiting reactions, its ability to precisely control film thickness and deposit uniformly and conformally is superior to PECVD, making it a preferred process to use for the deposition of the gate oxide, which is a key determinant of the MOSFET’s quality and behavior. Uniform deposition of a thin layer of gate oxide with ALD is essential to delivering an even electric field during MOSFET operation. Conversely, PECVD is an adequate option here, as it is a faster process than ALD and the thicker SiO2 layer it deposits helps to shield the MOSFET.
Graphical representation of the formation of Metal Contacts to the Device.
Testing of the MOSFETs
We successfully measured values for ID and VD, and were able to control those values by changing VG. In particular, when working with VG values in the range (0, 5), we observed saturation around the 700 mV mark of VD values. As expected, for VG = 0, saturation at the 1 mA threshold is achieved at a later point. When looking at the second MOSFET device at the 100 mA maximum level, we observe that ID values in the VD interval (0, 1) continue to increase and do not reach saturation. However, the placement of the curves, with curves corresponding to higher VG values showing higher ID values, matches the expected results demonstrated in Figure 6-9 from Streetman & Banerjee. See the full report in the Resources section for full testing results.
Families of IV curves for two MOSFET devices. From left to right, top to bottom: Family of IV curves for MOSFET device 1 for VG values -2 to +2 V; Family of IV curves for MOSFET device 1 for VG values 0 to +5 V and 1 mA maximum value; Family of IV curves for MOSFET device 1 for VG values -5 to 0 V and 1 mA maximum value; Family of IV curves for MOSFET device 1 for VG values -5 to +5 V and 100 mA maximum value; Family of IV curves for MOSFET device 2 for VG values -5 to +5 V and 100 mA maximum value.
Notes
This work was co-developed with the help of my teammates Mohib Jafri, Kedrick Brown, Robert Newman, and Elizabeth Suitor.
