Project Update
April 16, 2022
Implementing a MIPS multi-cycle processor
Using the skills of combinational and sequential logic needed for arithmetic circuits, memory, and timing, my efforts in CS141 efforts culminated in a capstone project: designing, testing, and synthesizing a MIPS multicycle processor.
Project Dates: April 2022 - May 2022
Built with: SystemVerilog, C++
Over the course of CS141: Computer Hardware, I designed an ALU, a multi-cycle processor to support the MIPS ISA and a controller for the traffic light system of a 4-way intersection on an FPGA. I also simulated a direct-mapped, fully associative and (n)-way set-associative caches in C to evaluate their efficiency for a given access pattern. As a capstone project, I designed, tested, and synthesized a MIPS multi-cycle processor. See the Resources section for the project code.
